The present invention relates generally to integrated circuits, and more particularly, to a clock multiplexer for generating a glitch-free clock signal.
Integrated circuits (ICs) such as a system on a chip (SoC) and application specific integrated circuits (ASICs) generally include two or more clock generators so that a malfunction or failure in one clock generator does not disable the system. Further, systems such as audio processors require inputs at different clock frequencies for tuning an audio frequency. Hence, such systems include several clock generators and a clock switching system. The clock generators provide clock signals at different frequencies and the clock switching system switches between the clock signals. The clock switching system includes a multiplexer to select and output one of the clock signals based on a select signal.
If a glitch occurs during a clock signal switching operation, data values within the IC may be corrupted. A known technique to avoid such glitches is to include a delay circuit in the clock switching system. During the switching operation, the delay circuit delays the clock output signal to prevent glitches from effecting the clock output signal. However, the delay prevents the clock switching system from switching from the currently selected clock signal to another clock signal before the currently selected clock signal goes inactive (i.e., when the currently selected clock signal is absent or is malfunctioning).
A known technique to overcome the above-mentioned problem is to include a monitoring circuit to detect the absence of the currently selected clock signal so that a controller or processor can change the select signal so that the multiplexer selects and outputs another clock signal. However, the addition of the monitoring circuit increases circuit area. Further, if the monitoring circuit malfunctions or fails, then there will be a failure in the clock switching system.
Another known technique includes resetting the clock generator when the currently selected clock signal is inactive. However, this technique is applicable only for a system that has two or more clock generators.
It would be advantageous to have a clock switching system that provides switching between multiple clock signals and avoids glitches.